DRFMT=B_0x0, CBDMAEN=B_0x0, CKSEN=B_0x0, CUMSK=B_0x0, INSEL=B_0x0, CHSEL=B_0x0, WFA=B_0x0, PTMSK=B_0x0, RXDMAEN=B_0x0, SPDIFRXEN=B_0x0, NBTR=B_0x0, CKSBKPEN=B_0x0, PMSK=B_0x0, VMSK=B_0x0, RXSTEO=B_0x0
SPDIFRX control register
| SPDIFRXEN | Peripheral block enable(1) This field is modified by software. It must be used to change the peripheral phase among the three possible states: STATE_IDLE, STATE_SYNC and STATE_RCV. It is not possible to transition from STATE_RCV to STATE_SYNC, the user must first go the STATE_IDLE. Note: it is possible to transition from STATE_IDLE to STATE_RCV: in that case the peripheral transitions from STATE_IDLE to STATE_SYNC and as soon as the synchronization is performed goes to STATE_RCV. 0 (B_0x0): Disable SPDIFRX (STATE_IDLE). 1 (B_0x1): Enable SPDIFRX synchronization only. 2 (B_0x2): FIELD Reserved 3 (B_0x3): Enable SPDIF receiver. |
| RXDMAEN | Receiver DMA enable for data flow(1) This bit is set/reset by software. Note: When this bit is set, the DMA request is made whenever the RXNE flag is set. 0 (B_0x0): DMA mode is disabled for reception. 1 (B_0x1): DMA mode is enabled for reception. |
| RXSTEO | Stereo mode(1) This bit is set/reset by software. Note: This bit is used in case of overrun situation in order to handle misalignment. 0 (B_0x0): The peripheral is in mono mode. 1 (B_0x1): The peripheral is in stereo mode. |
| DRFMT | RX data format(1) This bit is set/reset by software. 0 (B_0x0): Data samples are aligned in the right (LSB). 1 (B_0x1): Data samples are aligned in the left (MSB) 2 (B_0x2): Data sample are packed by setting two 16-bit sample into a 32-bit word. 3 (B_0x3): FIELD Reserved |
| PMSK | Mask parity error bit(1) This bit is set/reset by software. 0 (B_0x0): The parity error bit is copied into the SPDIFRX_FMTx_DR. 1 (B_0x1): The parity error bit is not copied into the SPDIFRX_FMTx_DR, a zero is written instead. |
| VMSK | Mask of validity bit(1) This bit is set/reset by software. 0 (B_0x0): The validity bit is copied into the SPDIFRX_FMTx_DR. 1 (B_0x1): The validity bit is not copied into the SPDIFRX_FMTx_DR, a zero is written instead. |
| CUMSK | Mask of channel status and user bits(1) This bit is set/reset by software. 0 (B_0x0): The channel status and user bits are copied into the SPDIFRX_FMTx_DR. 1 (B_0x1): The channel status and user bits are not copied into the SPDIFRX_FMTx_DR, zeros are written instead. |
| PTMSK | Mask of preamble type bits(1) This bit is set/reset by software. 0 (B_0x0): The preamble type bits are copied into the SPDIFRX_FMTx_DR. 1 (B_0x1): The preamble type bits are not copied into the SPDIFRX_FMTx_DR, zeros are written instead. |
| CBDMAEN | Control buffer DMA enable for control flow(1) This bit is set/reset by software. Note: When this bit is set, the DMA request is made whenever the CSRNE flag is set. 0 (B_0x0): DMA mode is disabled for reception of channel status and used data information. 1 (B_0x1): DMA mode is enabled for reception of channel status and used data information. |
| CHSEL | Channel selection(1) This bit is set/reset by software. 0 (B_0x0): The control flow takes the channel status from channel A. 1 (B_0x1): The control flow takes the channel status from channel B. |
| NBTR | Maximum allowed re-tries during synchronization phase(1) 0 (B_0x0): No re-try is allowed (only one attempt) 1 (B_0x1): 3 re-tries allowed 2 (B_0x2): 15 re-tries allowed 3 (B_0x3): 63 re-tries allowed |
| WFA | Wait for activity(1) This bit is set/reset by software. 0 (B_0x0): The SPDIFRX does not wait for activity on SPDIFRX_IN line before performing the synchronization. 1 (B_0x1): The SPDIFRX waits for activity on SPDIFRX_IN line (4 transitions) before performing the synchronization. |
| INSEL | SPDIFRX input selection other: reserved 0 (B_0x0): SPDIFRX_IN1 selected 1 (B_0x1): SPDIFRX_IN2 selected 2 (B_0x2): SPDIFRX_IN3 selected 3 (B_0x3): SPDIFRX_IN4 selected |
| CKSEN | Symbol clock enable This bit is set/reset by software. 0 (B_0x0): The SPDIFRX does not generate a symbol clock. 1 (B_0x1): The SPDIFRX generates a symbol clock. |
| CKSBKPEN | Backup symbol clock enable This bit is set/reset by software. 0 (B_0x0): The SPDIFRX does not generate a backup symbol clock. 1 (B_0x1): The SPDIFRX generates a backup symbol clock if CKSEN = 1. |