stm32 /stm32l0 /STM32L0x0 /PWR /CR

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Interpret as CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPSDSR)LPSDSR 0 (PDDS)PDDS 0 (CWUF)CWUF 0 (CSBF)CSBF 0 (DBP)DBP 0 (ULP)ULP 0 (FWU)FWU 0VOS0 (DS_EE_KOFF)DS_EE_KOFF 0 (LPRUN)LPRUN 0 (LPDS)LPDS

Description

power control register

Fields

LPSDSR

Low-power deepsleep/Sleep/Low-power run

PDDS

Power down deepsleep

CWUF

Clear wakeup flag

CSBF

Clear standby flag

DBP

Disable backup domain write protection

ULP

Ultra-low-power mode

FWU

Fast wakeup

VOS

Voltage scaling range selection

DS_EE_KOFF

Deep sleep mode with Flash memory kept off

LPRUN

Low power run mode

LPDS

Regulator in Low-power deepsleep mode

Links

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