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stm32 /stm32l0 /STM32L0x1 /RCC /CIER

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Interpret as CIER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSIRDYIE)LSIRDYIE 0 (LSERDYIE)LSERDYIE 0 (HSI16RDYIE)HSI16RDYIE 0 (HSERDYIE)HSERDYIE 0 (PLLRDYIE)PLLRDYIE 0 (MSIRDYIE)MSIRDYIE 0 (CSSLSE)CSSLSE

Description

Clock interrupt enable register

Fields

LSIRDYIE

LSI ready interrupt flag
LSERDYIE

LSE ready interrupt flag
HSI16RDYIE

HSI16 ready interrupt flag
HSERDYIE

HSE ready interrupt flag
PLLRDYIE

PLL ready interrupt flag
MSIRDYIE

MSI ready interrupt flag
CSSLSE

LSE CSS interrupt flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32