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stm32 /stm32l0 /STM32L0x1 /SYSCFG_COMP /CFGR2

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Interpret as CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FWDISEN)FWDISEN 0CAPA0 (I2C_PB6_FMP)I2C_PB6_FMP 0 (I2C_PB7_FMP)I2C_PB7_FMP 0 (I2C_PB8_FMP)I2C_PB8_FMP 0 (I2C_PB9_FMP)I2C_PB9_FMP 0 (I2C1_FMP)I2C1_FMP 0 (I2C2_FMP)I2C2_FMP

Description

SYSCFG configuration register 2

Fields

FWDISEN

Firewall disable bit
CAPA

Configuration of internal VLCD rail connection to optional external capacitor
I2C_PB6_FMP

Fm+ drive capability on PB6 enable bit
I2C_PB7_FMP

Fm+ drive capability on PB7 enable bit
I2C_PB8_FMP

Fm+ drive capability on PB8 enable bit
I2C_PB9_FMP

Fm+ drive capability on PB9 enable bit
I2C1_FMP

I2C1 Fm+ drive capability enable bit
I2C2_FMP

I2C2 Fm+ drive capability enable bit

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32