Regviz

stm32 /stm32l1 /STM32L100 /TIM6 /ARR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ARR

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https://regviz.com/r/stm32/stm32l1/STM32L100/TIM6/ARR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ARR

Description

TIM6 auto-reload register

Fields

ARR

Prescaler value

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32