stm32 /stm32l1 /STM32L152 /ADC /SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SR

31282724232019161512118743000000000000000000000000000000000000000000 (AWD)AWD0 (EOC)EOC0 (JEOC)JEOC0 (JSTRT)JSTRT0 (STRT)STRT0 (OVR)OVR0 (ADONS)ADONS0 (RCNR)RCNR0 (JCNR)JCNR

Description

status register

Fields

AWD

Analog watchdog flag

EOC

Regular channel end of conversion

JEOC

Injected channel end of conversion

JSTRT

Injected channel start flag

STRT

Regular channel start flag

OVR

Overrun

ADONS

ADC ON status

RCNR

Regular channel not ready

JCNR

Injected channel not ready

Links

()