stm32 /stm32l4+ /STM32L4P5 /RCC /PLLCFGR

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Interpret as PLLCFGR

31282724232019161512118743000000000000000000000000000000000000000000PLLSRC0PLLM0PLLN0 (PLLPEN)PLLPEN0 (PLLP)PLLP0 (PLLQEN)PLLQEN0PLLQ0 (PLLREN)PLLREN0PLLR0PLLPDIV

Description

PLL configuration register

Fields

PLLSRC

Main PLL, PLLSAI1 and PLLSAI2 entry clock source

PLLM

Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock

PLLN

Main PLL multiplication factor for VCO

PLLPEN

Main PLL PLLSAI3CLK output enable

PLLP

Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)

PLLQEN

Main PLL PLLUSB1CLK output enable

PLLQ

Main PLL division factor for PLLUSB1CLK(48 MHz clock)

PLLREN

Main PLL PLLCLK output enable

PLLR

Main PLL division factor for PLLCLK (system clock)

PLLPDIV

Main PLL division factor for PLLSAI2CLK

Links

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