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stm32 /stm32l4+ /STM32L4Q5 /LTCD /ISR

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Interpret as ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LIF)LIF 0 (FUIF)FUIF 0 (TERRIF)TERRIF 0 (RRIF)RRIF

Description

LTDC Interrupt Status Register

Fields

LIF

Line Interrupt flag
FUIF

FIFO Underrun Interrupt flag
TERRIF

Transfer Error interrupt flag
RRIF

Register Reload Interrupt Flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32