stm32 /stm32l4+ /STM32L4R5 /FLASH /OPTR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as OPTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDP0BOR_LEV 0 (nRST_STOP)nRST_STOP 0 (nRST_STDBY)nRST_STDBY 0 (nRST_SHDW)nRST_SHDW 0 (IWDG_SW)IWDG_SW 0 (IWDG_STOP)IWDG_STOP 0 (IWDG_STDBY)IWDG_STDBY 0 (WWDG_SW)WWDG_SW 0 (BFB2)BFB2 0 (DB1M)DB1M 0 (DBANK)DBANK 0 (nBOOT1)nBOOT1 0 (SRAM2_PE)SRAM2_PE 0 (SRAM2_RST)SRAM2_RST 0 (nSWBOOT0)nSWBOOT0 0 (nBOOT0)nBOOT0

Description

Flash option register

Fields

RDP

Read protection level

BOR_LEV

BOR reset Level

nRST_STOP

nRST_STOP

nRST_STDBY

nRST_STDBY

nRST_SHDW

nRST_SHDW

IWDG_SW

Independent watchdog selection

IWDG_STOP

Independent watchdog counter freeze in Stop mode

IWDG_STDBY

Independent watchdog counter freeze in Standby mode

WWDG_SW

Window watchdog selection

BFB2

Dual-bank boot

DB1M

Dual-bank on 1 Mbyte Flash memory devices

DBANK

DBANK

nBOOT1

Boot configuration

SRAM2_PE

SRAM2 parity check enable

SRAM2_RST

SRAM2 Erase when system reset

nSWBOOT0

Software BOOT0

nBOOT0

nBOOT0 option bit

Links

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