Regviz

stm32 /stm32l4 /STM32L412 /ADC12_Common /ADC_CDR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ADC_CDR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32l4/STM32L412/ADC12_Common/ADC_CDR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDATA_MST0RDATA_SLV

Description

ADC common regular data register for dual mode

Fields

RDATA_MST

Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to Section 16.4.32: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)) In MDMA = 11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0].
RDATA_SLV

Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Section 16.4.32: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN))

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32