Regviz

stm32 /stm32l4 /STM32L412 /LPTIM1 /CFGR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CFGR2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32l4/STM32L412/LPTIM1/CFGR2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IN1SEL 0IN2SEL

Description

configuration register 2

Fields

IN1SEL

LPTIM input 1 selection
IN2SEL

LPTIM input 2 selection

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32