Regviz

stm32 /stm32l4 /STM32L412 /RTC /MISR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MISR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32l4/STM32L412/RTC/MISR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALRAMF)ALRAMF 0 (ALRBMF)ALRBMF 0 (WUTMF)WUTMF 0 (TSMF)TSMF 0 (TSOVMF)TSOVMF 0 (ITSMF)ITSMF

Description

RTC masked interrupt status register

Fields

ALRAMF

Alarm A masked flag
ALRBMF

Alarm B masked flag
WUTMF

Wakeup timer masked flag
TSMF

Timestamp masked flag
TSOVMF

Timestamp overflow masked flag
ITSMF

Internal timestamp masked flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32