Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/stm32/stm32l4/STM32L412/TIM2/CNT#0x0
counter
Least significant part of counter value
Most significant part counter value
Value depends on IUFREMAP in TIMx_CR1.
https://github.com/modm-io/cmsis-svd-stm32