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stm32 /stm32l4 /STM32L476 /RCC /AHB2SMENR

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Interpret as AHB2SMENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GPIOASMEN)GPIOASMEN 0 (GPIOBSMEN)GPIOBSMEN 0 (GPIOCSMEN)GPIOCSMEN 0 (GPIODSMEN)GPIODSMEN 0 (GPIOESMEN)GPIOESMEN 0 (GPIOFSMEN)GPIOFSMEN 0 (GPIOGSMEN)GPIOGSMEN 0 (GPIOHSMEN)GPIOHSMEN 0 (GPIOISMEN)GPIOISMEN 0 (SRAM2SMEN)SRAM2SMEN 0 (OTGFSSMEN)OTGFSSMEN 0 (ADCFSSMEN)ADCFSSMEN 0 (DCMISMEN)DCMISMEN 0 (AESSMEN)AESSMEN 0 (HASH1SMEN)HASH1SMEN 0 (RNGSMEN)RNGSMEN

Description

AHB2 peripheral clocks enable in Sleep and Stop modes register

Fields

GPIOASMEN

IO port A clocks enable during Sleep and Stop modes
GPIOBSMEN

IO port B clocks enable during Sleep and Stop modes
GPIOCSMEN

IO port C clocks enable during Sleep and Stop modes
GPIODSMEN

IO port D clocks enable during Sleep and Stop modes
GPIOESMEN

IO port E clocks enable during Sleep and Stop modes
GPIOFSMEN

IO port F clocks enable during Sleep and Stop modes
GPIOGSMEN

IO port G clocks enable during Sleep and Stop modes
GPIOHSMEN

IO port H clocks enable during Sleep and Stop modes
GPIOISMEN

IO port I clocks enable during Sleep and Stop modes
SRAM2SMEN

SRAM2 interface clocks enable during Sleep and Stop modes
OTGFSSMEN

OTG full speed clocks enable during Sleep and Stop modes
ADCFSSMEN

ADC clocks enable during Sleep and Stop modes
DCMISMEN

DCMI clock enable during Sleep and Stop modes
AESSMEN

AES accelerator clocks enable during Sleep and Stop modes
HASH1SMEN

HASH clock enable during Sleep and Stop modes
RNGSMEN

Random Number Generator clocks enable during Sleep and Stop modes

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32