RDY=B_0x0, SOF=B_0x0, ENS=B_0x0, FCRSF=B_0x0, UDD=B_0x0, UDR=B_0x0
LCD status register
| ENS | LCD enabled status This bit is set and cleared by hardware. It indicates the LCD controller status. The ENS bit is set immediately when the LCDEN bit in the LCD_CR goes from 0 to 1. On deactivation it reflects the real status of LCD so it becomes 0 at the end of the last displayed frame. 0 (B_0x0): LCD controller disabled 1 (B_0x1): LCD controller enabled |
| SOF | Start-of-frame flag This bit is set by hardware at the beginning of a new frame, at the same time as the display data is updated. It is cleared by writing a 1 to the SOFC bit in the LCD_CLR register. The bit clear has priority over the set. 0 (B_0x0): No event 1 (B_0x1): Start-of-frame event occurred. |
| UDR | Update display request 0 (B_0x0): No effect 1 (B_0x1): Update display request |
| UDD | Update display done This bit is set by hardware. It is cleared by writing 1 to the UDDC bit in the LCD_CLR register. The bit set has priority over the clear. If the device is in Stop mode (PCLK not provided), UDD does not generate an interrupt even if UDDIE = 1. If the display is not enabled the UDD interrupt never occurs. 0 (B_0x0): No event 1 (B_0x1): Update Display Request done. |
| RDY | Ready flag This bit is set and cleared by hardware. It indicates the status of the step-up converter. 0 (B_0x0): Not ready 1 (B_0x1): Step-up converter is enabled and ready to provide the correct voltage. |
| FCRSF | LCD frame control register synchronization flag This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register. 0 (B_0x0): LCD frame control register not yet synchronized 1 (B_0x1): LCD frame control register synchronized |