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stm32 /stm32l4 /STM32L4x3 /RCC /APB1RSTR1

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Interpret as APB1RSTR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM2RST)TIM2RST 0 (TIM6RST)TIM6RST 0 (TIM7RST)TIM7RST 0 (LCDRST)LCDRST 0 (SPI2RST)SPI2RST 0 (SPI3RST)SPI3RST 0 (USART2RST)USART2RST 0 (USART3RST)USART3RST 0 (UART4RST)UART4RST 0 (UART5RST)UART5RST 0 (I2C1RST)I2C1RST 0 (I2C2RST)I2C2RST 0 (I2C3RST)I2C3RST 0 (CAN1RST)CAN1RST 0 (PWRRST)PWRRST 0 (DAC1RST)DAC1RST 0 (OPAMPRST)OPAMPRST 0 (LPTIM1RST)LPTIM1RST

Description

APB1 peripheral reset register 1

Fields

TIM2RST

TIM2 timer reset
TIM6RST

TIM6 timer reset
TIM7RST

TIM7 timer reset
LCDRST

LCD interface reset
SPI2RST

SPI2 reset
SPI3RST

SPI3 reset
USART2RST

USART2 reset
USART3RST

USART3 reset
UART4RST

UART4 reset
UART5RST

UART5 reset
I2C1RST

I2C1 reset
I2C2RST

I2C2 reset
I2C3RST

I2C3 reset
CAN1RST

CAN1 reset
PWRRST

Power interface reset
DAC1RST

DAC1 interface reset
OPAMPRST

OPAMP interface reset
LPTIM1RST

Low Power Timer 1 reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32