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stm32 /stm32l5 /STM32L552 /DFSDM1 /CH0DLYR

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Interpret as CH0DLYR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLSSKP

Description

DFSDM channel y delay register

Fields

PLSSKP

Pulses to skip for input data skipping function

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32