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stm32 /stm32l5 /STM32L552 /FLASH /NSCR

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Interpret as NSCR

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https://regviz.com/r/stm32/stm32l5/STM32L552/FLASH/NSCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NSPG)NSPG 0 (NSPER)NSPER 0 (NSMER1)NSMER1 0NSPNB0 (NSBKER)NSBKER 0 (NSMER2)NSMER2 0 (NSSTRT)NSSTRT 0 (OPTSTRT)OPTSTRT 0 (NSEOPIE)NSEOPIE 0 (NSERRIE)NSERRIE 0 (OBL_LAUNCH)OBL_LAUNCH 0 (OPTLOCK)OPTLOCK 0 (NSLOCK)NSLOCK

Description

Flash non-secure control register

Fields

NSPG

NSPG
NSPER

NSPER
NSMER1

NSMER1
NSPNB

NSPNB
NSBKER

NSBKER
NSMER2

NSMER2
NSSTRT

Options modification start
OPTSTRT

Options modification start
NSEOPIE

NSEOPIE
NSERRIE

NSERRIE
OBL_LAUNCH

Force the option byte loading
OPTLOCK

Options Lock
NSLOCK

NSLOCK

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32