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stm32 /stm32l5 /STM32L552 /GTZC_TZSC /TZSC_SECCFGR2

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Interpret as TZSC_SECCFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM8SEC)TIM8SEC 0 (USART1SEC)USART1SEC 0 (TIM15SEC)TIM15SEC 0 (TIM16SEC)TIM16SEC 0 (TIM17SEC)TIM17SEC 0 (SAI1SEC)SAI1SEC 0 (SAI2SEC)SAI2SEC 0 (DFSDM1SEC)DFSDM1SEC 0 (CRCSEC)CRCSEC 0 (TSCSEC)TSCSEC 0 (ICACHESEC)ICACHESEC 0 (ADCSEC)ADCSEC 0 (AESSEC)AESSEC 0 (HASHSEC)HASHSEC 0 (RNGSEC)RNGSEC 0 (PKASEC)PKASEC 0 (SDMMC1SEC)SDMMC1SEC 0 (FSMC_REGSEC)FSMC_REGSEC 0 (OCTOSPI1_REGSEC)OCTOSPI1_REGSEC

Description

TZSC secure configuration register 2

Fields

TIM8SEC

TIM8SEC
USART1SEC

USART1SEC
TIM15SEC

TIM15SEC
TIM16SEC

TIM16SEC
TIM17SEC

TIM17SEC
SAI1SEC

SAI1SEC
SAI2SEC

SAI2SEC
DFSDM1SEC

DFSDM1SEC
CRCSEC

CRCSEC
TSCSEC

TSCSEC
ICACHESEC

ICACHESEC
ADCSEC

ADCSEC
AESSEC

AESSEC
HASHSEC

HASHSEC
RNGSEC

RNGSEC
PKASEC

PKASEC
SDMMC1SEC

SDMMC1SEC
FSMC_REGSEC

FSMC_REGSEC
OCTOSPI1_REGSEC

OCTOSPI1_REGSEC

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32