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stm32 /stm32l5 /STM32L552 /OCTOSPI1 /HLCR

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Interpret as HLCR

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31282724232019161512118743000000000000000000000000000000000000000000 (LM)LM0 (WZL)WZL0TACC0TRWR

Description

HyperBus latency configuration register

Fields

LM

Latency mode
WZL

Write zero latency
TACC

Access time
TRWR

Read write recovery time

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32