Regviz

stm32 /stm32l5 /STM32L552 /TIM7 /ARR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ARR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32l5/STM32L552/TIM7/ARR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ARR_bit0

Description

auto-reload register

Fields

ARR_bit0

ARR_bit0

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32