Regviz

stm32 /stm32l5 /STM32L552 /TIM8 /OR1

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Interpret as OR1

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https://regviz.com/r/stm32/stm32l5/STM32L552/TIM8/OR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TI1_RMP)TI1_RMP

Description

DMA address for full transfer

Fields

TI1_RMP

Input Capture 1 remap

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32