Regviz

stm32 /stm32n6 /STM32N645 /ADC1 /ADC_DR

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Interpret as ADC_DR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDATA

Description

ADC regular data register

Fields

RDATA

Regular data converted

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32