stm32 /stm32n6 /STM32N645 /ADF /ADF_DFLT0CR

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Interpret as ADF_DFLT0CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DFLTEN 0 (B_0x0)DMAEN 0 (B_0x0)FTH 0 (B_0x0)ACQMOD 0 (B_0x0)TRGSENS 0 (B_0x0)TRGSRC0 (B_0x0)NBDIS0 (B_0x0)DFLTRUN 0 (B_0x0)DFLTACTIVE

DFLTACTIVE=B_0x0, TRGSRC=B_0x0, NBDIS=B_0x0, DFLTRUN=B_0x0, FTH=B_0x0, DFLTEN=B_0x0, TRGSENS=B_0x0, ACQMOD=B_0x0, DMAEN=B_0x0

Description

ADF digital filter control register 0

Fields

DFLTEN

DFLT0 enable

0 (B_0x0): Acquisition immediately stopped

1 (B_0x1): Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x.

DMAEN

DMA requests enable

0 (B_0x0): DMA interface for the corresponding digital filter disabled

1 (B_0x1): DMA interface for the corresponding digital filter enabled

FTH

RXFIFO threshold selection

0 (B_0x0): RXFIFO threshold event generated when the RXFIFO is not empty

1 (B_0x1): RXFIFO threshold event generated when the RXFIFO is half-full

ACQMOD

DFLT0 trigger mode

0 (B_0x0): Asynchronous continuous acquisition mode

1 (B_0x1): Asynchronous single-shot acquisition mode

2 (B_0x2): Synchronous continuous acquisition mode

3 (B_0x3): Synchronous single-shot acquisition mode

4 (B_0x4): Window continuous acquisition mode

TRGSENS

DFLT0 trigger sensitivity selection

0 (B_0x0): A rising edge event triggers the acquisition.

1 (B_0x1): A falling edge even triggers the acquisition.

TRGSRC

DFLT0 trigger signal selection

0 (B_0x0): TRGO selected

2 (B_0x2): adf_trgi selected

NBDIS

Number of samples to be discarded

0 (B_0x0): No sample discarded

1 (B_0x1): 1 sample discarded

DFLTRUN

DFLT0 run status flag

0 (B_0x0): DFLT0 not running and ready to accept a new trigger event

1 (B_0x1): DFLT0running

DFLTACTIVE

DFLT0 active flag

0 (B_0x0): DFLT0 not active (can be re-enabled again, via DFLTEN bit, if needed)

1 (B_0x1): DFLT0 active

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