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stm32 /stm32n6 /STM32N645 /ADF /ADF_DLY0CR

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Interpret as ADF_DLY0CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SKPDLY0 (B_0x0)SKPBF

SKPBF=B_0x0, SKPDLY=B_0x0

Description

ADF delay control register 0

Fields

SKPDLY

Delay to apply to a bitstream

0 (B_0x0): No input sample skipped

1 (B_0x1): 1 input sample skipped
SKPBF

Skip busy flag

0 (B_0x0): ADF ready to accept a new value into SKPDLY[6:0]

1 (B_0x1): Last valid SKPDLY[6:0] still under precessing

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32