CM=B_0x0, CAPTURE=B_0x0, VSPOL=B_0x0, ENABLE=B_0x0, LSM=B_0x0, EDM=B_0x0, OEBS=B_0x0, BSM=B_0x0, FCRC=B_0x0, HSPOL=B_0x0, PCKPOL=B_0x0, ESS=B_0x0, JPEG=B_0x0, OELS=B_0x0, CROP=B_0x0
DCMI control register
| CAPTURE | Capture enable 0 (B_0x0): Capture disabled 1 (B_0x1): Capture enabled |
| CM | Capture mode 0 (B_0x0): Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA. 1 (B_0x1): Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset. |
| CROP | Crop feature 0 (B_0x0): The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four. 1 (B_0x1): Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured. |
| JPEG | JPEG format 0 (B_0x0): Uncompressed video format 1 (B_0x1): This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode. |
| ESS | Embedded synchronization select 0 (B_0x0): Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals. 1 (B_0x1): Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow. |
| PCKPOL | Pixel clock polarity 0 (B_0x0): Falling edge active 1 (B_0x1): Rising edge active |
| HSPOL | Horizontal synchronization polarity 0 (B_0x0): DCMI_HSYNC active low 1 (B_0x1): DCMI_HSYNC active high |
| VSPOL | Vertical synchronization polarity 0 (B_0x0): DCMI_VSYNC active low 1 (B_0x1): DCMI_VSYNC active high |
| FCRC | Frame capture rate control 0 (B_0x0): All frames are captured. 1 (B_0x1): Every alternate frame captured (50% bandwidth reduction) 2 (B_0x2): One frame out of four captured (75% bandwidth reduction) |
| EDM | Extended data mode 0 (B_0x0): Interface captures 8-bit data on every pixel clock. 1 (B_0x1): Interface captures 10-bit data on every pixel clock. 2 (B_0x2): Interface captures 12-bit data on every pixel clock. 3 (B_0x3): Interface captures 14-bit data on every pixel clock. |
| ENABLE | DCMI enable 0 (B_0x0): DCMI disabled 1 (B_0x1): DCMI enabled |
| BSM | Byte Select mode 0 (B_0x0): Interface captures all received data. 1 (B_0x1): Interface captures every other byte from the received data. 2 (B_0x2): Interface captures one byte out of four. 3 (B_0x3): Interface captures two bytes out of four. |
| OEBS | Odd/Even Byte Select (Byte Select Start) 0 (B_0x0): Interface captures first data (byte or double byte) from the frame/line start, second one being dropped. 1 (B_0x1): Interface captures second data (byte or double byte) from the frame/line start, first one being dropped. |
| LSM | Line Select mode 0 (B_0x0): Interface captures all received lines. 1 (B_0x1): Interface captures one line out of two. |
| OELS | Odd/Even Line Select (Line Select Start) 0 (B_0x0): Interface captures first line after the frame start, second one being dropped. 1 (B_0x1): Interface captures second line from the frame start, first one being dropped. |