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stm32 /stm32n6 /STM32N645 /DCMIPP /DCMIPP_CMCR

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Interpret as DCMIPP_CMCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)INSEL 0 (B_0x0)PSFC 0 (CFC)CFC 0 (B_0x0)SWAPRB

SWAPRB=B_0x0, PSFC=B_0x0, INSEL=B_0x0

Description

DCMIPP common configuration register

Fields

INSEL

input selection

0 (B_0x0): DCMI

1 (B_0x1): CSI-2
PSFC

Pipe selection for the frame counter

0 (B_0x0): Frame counter mapped to Pipe0

1 (B_0x1): Frame counter mapped to Pipe1

2 (B_0x2): Frame counter mapped to Pipe2
CFC

Clear frame counter
SWAPRB

Swap R/U and B/V

0 (B_0x0): RGB/VYU

1 (B_0x1): BGR/UYV

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32