Regviz

stm32 /stm32n6 /STM32N645 /DCMIPP /DCMIPP_PRIER

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DCMIPP_PRIER

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/DCMIPP/DCMIPP_PRIER#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ERRIE

ERRIE=B_0x0

Description

DCMIPP parallel interface interrupt enable register

Fields

ERRIE

Synchronization error interrupt enable

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated if the embedded synchronization codes are not received in the correct order.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32