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stm32 /stm32n6 /STM32N645 /DCMIPP /DCMIPP_PRSR

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Interpret as DCMIPP_PRSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ERRF 0 (B_0x0)HSYNC 0 (B_0x0)VSYNC

HSYNC=B_0x0, VSYNC=B_0x0, ERRF=B_0x0

Description

DCMIPP parallel interface status register

Fields

ERRF

Synchronization error raw interrupt status

0 (B_0x0): No synchronization error detected

1 (B_0x1): Embedded synchronization characters are not received in the correct order.
HSYNC

This bit gives the state of the HSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in HPOL bit, and cleared otherwise.

0 (B_0x0): Active line

1 (B_0x1): Synchronization between lines
VSYNC

This bit gives the state of the VSYNC pin with the correct programmed polarity if ENABLE bit is set into the DCMIPP_PRCR register and if the pixel clock is received. It is set during the blanking period whatever the polarity selected in VPOL bit, and cleared otherwise.

0 (B_0x0): Active frame

1 (B_0x1): Synchronization between frames

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32