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stm32 /stm32n6 /STM32N645 /DTS /DTS_TS0HILORESETR

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Interpret as DTS_TS0HILORESETR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SMPL_LO_SET)SMPL_LO_SET 0 (SMPL_HI_CLR)SMPL_HI_CLR

Description

DTS TS0 high/low reset register

Fields

SMPL_LO_SET

Sample Low Set
SMPL_HI_CLR

Sample high clear 0

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32