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stm32 /stm32n6 /STM32N645 /ETH /ETH_DMAC0MFCR

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Interpret as ETH_DMAC0MFCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MFC0 (MFCO)MFCO

Description

Channel 0 missed frame count register

Fields

MFC

Dropped Packet Counters
MFCO

Overflow status of the MFC Counter

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32