ETH_DMAC1RXCR

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Interpret as ETH_DMAC1RXCR

Channel 1 receive control register

SR	Start or Stop Receive
RBSZ	Receive Buffer size
RXPBL	Receive Programmable Burst Length
RQOS	Rx AXI4 QOS.
RPF	DMA Rx Channel x Packet Flush

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