PS=B_0x0, IPG=B_0x0, FES=B_0x0, BL=B_0x0, PRELEN=B_0x0
Operating mode configuration register
| RE | Receiver Enable |
| TE | Transmitter Enable |
| PRELEN | Preamble Length for Transmit packets 0 (B_0x0): 7 bytes of preamble 1 (B_0x1): 5 bytes of preamble 2 (B_0x2): 3 bytes of preamble |
| DC | Deferral Check |
| BL | Back-Off Limit 0 (B_0x0): k= min (n, 10) 1 (B_0x1): k = min (n, 8) 2 (B_0x2): k = min (n, 4) 3 (B_0x3): k = min (n, 1) |
| DR | Disable Retry |
| DCRS | Disable Carrier Sense During Transmission |
| DO | Disable Receive Own |
| ECRSFD | Enable Carrier Sense Before Transmission in Full-duplex mode |
| LM | Loopback Mode |
| DM | Duplex Mode |
| FES | MAC Speed 0 (B_0x0): 10 Mbps 1 (B_0x1): 100 Mbps |
| PS | Port Select 0 (B_0x0): For 1000 Mbps operations 1 (B_0x1): For 10 or 100 Mbps operations |
| JE | Jumbo Packet Enable |
| JD | Jabber Disable |
| BE | Packet Burst Enable |
| WD | Watchdog Disable |
| ACS | Automatic Pad or CRC Stripping |
| CST | CRC stripping for Type packets |
| S2KP | IEEE 802.3as Support for 2K Packets |
| GPSLCE | Giant Packet Size Limit Control Enable |
| IPG | Inter-Packet Gap 0 (B_0x0): 96 bit times 1 (B_0x1): 88 bit times 2 (B_0x2): 80 bit times 7 (B_0x7): 40 bit times |
| IPC | Checksum Offload |
| SARC | Source Address Insertion or Replacement Control 2 (B_0x2): the MAC inserts the content of the MAC Address 0 registers (MAC Address 0 high register (ETH_MACA0HR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets. 3 (B_0x3): the MAC replaces the content of the MAC Address 0 registers (MAC Address 0 high register (ETH_MACA0HR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets. 6 (B_0x6): the MAC inserts the content of the MAC Address 1 registers (MAC Address x high register (ETH_MACAxHR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets 7 (B_0x7): the MAC replaces the content of the MAC Address 1 registers (MAC Address x high register (ETH_MACAxHR) and MAC Address x low register (ETH_MACAxLR)) in the SA field of all transmitted packets. |
| ARPEN | ARP Offload Enable |