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stm32 /stm32n6 /STM32N645 /ETH /ETH_MACDR

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Interpret as ETH_MACDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RPESTS)RPESTS 0RFCFCSTS 0 (TPESTS)TPESTS 0 (B_0x0)TFCSTS

TFCSTS=B_0x0

Description

Debug register

Fields

RPESTS

MAC GMII or MII Receive Protocol Engine Status
RFCFCSTS

MAC Receive Packet Controller FIFO Status
TPESTS

MAC GMII or MII Transmit Protocol Engine Status
TFCSTS

MAC Transmit Packet Controller Status

0 (B_0x0): Idle state

1 (B_0x1): Waiting for one of the following:

2 (B_0x2): Generating and transmitting a Pause control packet (in Full-duplex mode)

3 (B_0x3): Transferring input packet for transmission

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32