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stm32 /stm32n6 /STM32N645 /ETH /ETH_MACPPSI0R

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Interpret as ETH_MACPPSI0R

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PPSINT0

Description

PPS 0 interval register

Fields

PPSINT0

PPS Output Signal Interval

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32