Regviz

stm32 /stm32n6 /STM32N645 /ETH /ETH_MTLOMR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ETH_MTLOMR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/ETH/ETH_MTLOMR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DTXSTS)DTXSTS 0 (B_0x0)RAA 0 (B_0x0)SCHALG 0 (CNTPRST)CNTPRST 0 (CNTCLR)CNTCLR

RAA=B_0x0, SCHALG=B_0x0

Description

Operating mode Register

Fields

DTXSTS

Drop Transmit Status
RAA

Receive Arbitration Algorithm

0 (B_0x0): Strict priority (SP). Queue 0 has the lowest priority and the last queue has the highest priority.

1 (B_0x1): Weighted Strict priority (WSP)
SCHALG

Tx Scheduling Algorithm

0 (B_0x0): Weighted round robin (WRR) algorithm

3 (B_0x3): Strict priority (SP) algorithm.
CNTPRST

Counters Preset
CNTCLR

Counters Reset

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32