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stm32 /stm32n6 /STM32N645 /ETH /ETH_MTLRXQ1DR

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Interpret as ETH_MTLRXQ1DR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RWCSTS)RWCSTS 0 (B_0x0)RRCSTS 0 (B_0x0)RXQSTS 0PRXQ

RXQSTS=B_0x0, RRCSTS=B_0x0

Description

R1 queue 1 debug register

Fields

RWCSTS

MTL Rx Queue Write Controller Active Status
RRCSTS

MTL Rx Queue Read Controller State

0 (B_0x0): Idle state

1 (B_0x1): Reading packet data

2 (B_0x2): Reading packet status (or timestamp)

3 (B_0x3): Flushing the packet data and status
RXQSTS

MTL Rx Queue Fill-Level Status

0 (B_0x0): Rx queue empty

1 (B_0x1): Rx queue fill-level below flow-control deactivate threshold

2 (B_0x2): Rx queue fill-level above flow-control activate threshold

3 (B_0x3): Rx queue full
PRXQ

Number of Packets in Receive Queue

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32