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stm32 /stm32n6 /STM32N645 /ETH /ETH_MTLRXQDMAMR

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Interpret as ETH_MTLRXQDMAMR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)Q0MDMACH 0 (Q0DDMACH)Q0DDMACH 0 (B_0x0)Q1MDMACH 0 (Q1DDMACH)Q1DDMACH

Q1MDMACH=B_0x0, Q0MDMACH=B_0x0

Description

Rx Queue and DMA Channel Mapping Register

Fields

Q0MDMACH

Queue 0 Mapped to DMA Channel

0 (B_0x0): DMA Channel 0

1 (B_0x1): DMA Channel 1
Q0DDMACH

Queue 0 Enabled for DA-based DMA Channel Selection
Q1MDMACH

Queue 1 Mapped to DMA Channel

0 (B_0x0): DMA Channel 0

1 (B_0x1): DMA Channel 1
Q1DDMACH

Queue 1 Enabled for DA-based DMA Channel Selection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32