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stm32 /stm32n6 /STM32N645 /ETH /ETH_MTLTXQ1ECR

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Interpret as ETH_MTLTXQ1ECR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AVALG)AVALG 0 (CC)CC 0 (B_0x0)SLC

SLC=B_0x0

Description

Tx queue 1 ETS control Register

Fields

AVALG

AV Algorithm
CC

Credit Control
SLC

Slot Count

0 (B_0x0): 1 Slot

1 (B_0x1): 2 Slots

2 (B_0x2): 4 Slots

3 (B_0x3): 8 Slots

4 (B_0x4): 16 Slots

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32