stm32 /stm32n6 /STM32N645 /FDCAN1 /FDCAN_PSR

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Interpret as FDCAN_PSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LEC0 (B_0x0)ACT0 (B_0x0)EP 0 (B_0x0)EW 0 (B_0x0)BO 0DLEC0 (B_0x0)RESI 0 (B_0x0)RBRS 0 (B_0x0)REDL 0 (B_0x0)PXE 0TDCV

EP=B_0x0, LEC=B_0x0, RESI=B_0x0, EW=B_0x0, REDL=B_0x0, RBRS=B_0x0, ACT=B_0x0, BO=B_0x0, PXE=B_0x0

Description

FDCAN protocol status register

Fields

LEC

Last error code

0 (B_0x0): No error: No error occurred since LEC has been reset by successful reception or transmission.

1 (B_0x1): Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.

2 (B_0x2): Form error: A fixed format part of a received frame has the wrong format.

3 (B_0x3): AckError: The message transmitted by the FDCAN was not acknowledged by another node.

4 (B_0x4): Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant.

5 (B_0x5): Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).

6 (B_0x6): CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.

7 (B_0x7): NoChange: Any read access to the protocol status register re-initializes the LEC to 7. When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the protocol status register.

ACT

Activity

0 (B_0x0): Synchronizing: node is synchronizing on CAN communication

1 (B_0x1): Idle: node is neither receiver nor transmitter

2 (B_0x2): Receiver: node is operating as receiver

3 (B_0x3): Transmitter: node is operating as transmitter

EP

Error passive

0 (B_0x0): The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected

1 (B_0x1): The FDCAN is in the Error_Passive state

EW

Warning status

0 (B_0x0): Both error counters are below the Error_Warning limit of 96

1 (B_0x1): At least one of error counter has reached the Error_Warning limit of 96

BO

Bus_Off status

0 (B_0x0): The FDCAN is not Bus_Off

1 (B_0x1): The FDCAN is in Bus_Off state

DLEC

Data last error code

RESI

ESI flag of last received FDCAN message

0 (B_0x0): Last received FDCAN message did not ha ve its ESI flag set

1 (B_0x1): Last received FDCAN message had its ESI flag set

RBRS

BRS flag of last received FDCAN message

0 (B_0x0): Last received FDCAN message did not have its BRS flag set

1 (B_0x1): Last received FDCAN message had its BRS flag set

REDL

Received FDCAN message

0 (B_0x0): Since this bit was reset by the CPU, no FDCAN message has been received

1 (B_0x1): Message in FDCAN format with EDL flag set has been received

PXE

Protocol exception event

0 (B_0x0): No protocol exception event occurred since last read access

1 (B_0x1): Protocol exception event occurred

TDCV

Transmitter delay compensation value

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