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stm32 /stm32n6 /STM32N645 /FMC1 /FMC_CSQAR2

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Interpret as FMC_CSQAR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADDC50SAO

Description

FMC NAND command sequencer address register 2

Fields

ADDC5

Address Cycle 5
SAO

Spare Area Address Offset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32