DMASEN=B_0x0, RCMD2EN=B_0x0, RCMD2T=B_0x0, SQSDTEN=B_0x0, RCMD1T=B_0x0
FMC NAND command sequencer configuration register 2
| SQSDTEN | Sequencer spare data transfer enable 0 (B_0x0): ECC disabled and spare data area not accessed by the sequencer 1 (B_0x1): ECC enabled and spare data area read or programmed by the sequencer after each sector transfer |
| RCMD2EN | Random Command 2 sequencer enable 0 (B_0x0): Command 2 not issued. 1 (B_0x1): Command 2 (CMD2SQ[7:0]) issued by the command sequencer to NAND flash memory after the address cycle. |
| DMASEN | Command sequencer DMA request decoding status enable 0 (B_0x0): No DMA request used for ECC status registers transfer 1 (B_0x1): A DMA request used for ECC status registers transfer |
| RCMD1 | Random Command 1 sequencer |
| RCMD2 | Random Command 2 sequencer |
| RCMD1T | Command 1 sequencer timings 0 (B_0x0): CMD1 issued with the timings programmed in FMC_PMEM 1 (B_0x1): CMD1 issued with the timings programmed in FMC_PATT |
| RCMD2T | Command 1 sequencer timings 0 (B_0x0): CMD1 issued with the timings programmed in FMC_PMEM 1 (B_0x1): CMD1 issued with the timings programmed in FMC_PATT |