stm32 /stm32n6 /STM32N645 /FMC1 /FMC_SDCMR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FMC_SDCMR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)MODE0 (B_0x0)DS2 0 (B_0x0)DS1 0 (B_0x0)NRFS0MRD

NRFS=B_0x0, DS1=B_0x0, DS2=B_0x0, MODE=B_0x0

Description

SDRAM command mode register

Fields

MODE

Command mode

0 (B_0x0): Normal mode command (NRM)

2 (B_0x2): Precharge all banks command (PALL)

3 (B_0x3): Refresh command (REF)

4 (B_0x4): Load mode register command (LMR)

5 (B_0x5): Self-refresh command (SR)

6 (B_0x6): Power-down command (PD)

DS2

Command targeting SDRAM device 2

0 (B_0x0): Command not issued to SDRAM device 2

1 (B_0x1): Command issued to SDRAM device 2

DS1

Command targeting SDRAM device 1

0 (B_0x0): Command not issued to SDRAM device 1

1 (B_0x1): Command issued to SDRAM device 1

NRFS

Number of Refresh commands

0 (B_0x0): 1 Refresh cycle

1 (B_0x1): 2 Refresh cycles

14 (B_0xE): 15 Refresh cycles

15 (B_0xF): 16 Refresh cycles

MRD

Mode register definition

Links

()