RegViz: Visualize GPIOA_PIOCFGRL Bitfield

stm32 /stm32n6 /STM32N645 /GPIOA /GPIOA_PIOCFGRL

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Interpret as GPIOA_PIOCFGRL

PIOCFG0=B_0x0, PIOCFG2=B_0x0, PIOCFG7=B_0x0, PIOCFG1=B_0x0, PIOCFG5=B_0x0, PIOCFG3=B_0x0, PIOCFG6=B_0x0, PIOCFG4=B_0x0

Description

GPIO port A PIO control low register

Fields

PIOCFG0	Port x I/O pin y configuration 0 (B_0x0): Input and output data are not synchronized or retimed on clock edges. 1 (B_0x1): Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk).
PIOCFG1	Port x I/O pin y configuration 0 (B_0x0): Input and output data are not synchronized or retimed on clock edges. 1 (B_0x1): Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk).
PIOCFG2	Port x I/O pin y configuration 0 (B_0x0): Input and output data are not synchronized or retimed on clock edges. 1 (B_0x1): Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk).
PIOCFG3	Port x I/O pin y configuration 0 (B_0x0): Input and output data are not synchronized or retimed on clock edges. 1 (B_0x1): Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk).
PIOCFG4	Port x I/O pin y configuration 0 (B_0x0): Input and output data are not synchronized or retimed on clock edges. 1 (B_0x1): Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk).
PIOCFG5	Port x I/O pin y configuration 0 (B_0x0): Input and output data are not synchronized or retimed on clock edges. 1 (B_0x1): Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk).
PIOCFG6	Port x I/O pin y configuration 0 (B_0x0): Input and output data are not synchronized or retimed on clock edges. 1 (B_0x1): Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk).
PIOCFG7	Port x I/O pin y configuration 0 (B_0x0): Input and output data are not synchronized or retimed on clock edges. 1 (B_0x1): Input and output data are retimed to either rising or falling clock edge depending on PIOCFG[2] value (cfg_invertclk).

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