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stm32 /stm32n6 /STM32N645 /GPIOB /GPIOB_HWCFGR2

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Interpret as GPIOB_HWCFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0AFRL_RES

Description

GPIO port B hardware configuration register 2

Fields

AFRL_RES

AF register low reset value

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32