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stm32 /stm32n6 /STM32N645 /GPIOH /GPIOH_HWCFGR1

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Interpret as GPIOH_HWCFGR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0AFRH_RES

Description

GPIO port H hardware configuration register 1

Fields

AFRH_RES

AF register high reset value

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32