stm32 /stm32n6 /STM32N645 /HPDMA /HPDMA_SECCFGR

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Interpret as HPDMA_SECCFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SEC0 0 (B_0x0)SEC1 0 (B_0x0)SEC2 0 (B_0x0)SEC3 0 (B_0x0)SEC4 0 (B_0x0)SEC5 0 (B_0x0)SEC6 0 (B_0x0)SEC7 0 (B_0x0)SEC8 0 (B_0x0)SEC9 0 (B_0x0)SEC10 0 (B_0x0)SEC11 0 (B_0x0)SEC12 0 (B_0x0)SEC13 0 (B_0x0)SEC14 0 (B_0x0)SEC15

SEC10=B_0x0, SEC1=B_0x0, SEC14=B_0x0, SEC13=B_0x0, SEC2=B_0x0, SEC11=B_0x0, SEC9=B_0x0, SEC7=B_0x0, SEC4=B_0x0, SEC12=B_0x0, SEC5=B_0x0, SEC0=B_0x0, SEC15=B_0x0, SEC8=B_0x0, SEC3=B_0x0, SEC6=B_0x0

Description

HPDMA secure configuration register

Fields

SEC0

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC1

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC2

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC3

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC4

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC5

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC6

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC7

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC8

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC9

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC10

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC11

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC12

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC13

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC14

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

SEC15

secure state of channel x

0 (B_0x0): non-secure

1 (B_0x1): secure

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