stm32 /stm32n6 /STM32N645 /I3C1 /I3C_GETMXDSR

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Interpret as I3C_GETMXDSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HOFFAS 0 (B_0x0)FMT0RDTURN0 (B_0x0)TSCO

HOFFAS=B_0x0, TSCO=B_0x0, FMT=B_0x0

Description

I3C get capability register

Fields

HOFFAS

Controller hand-off activity state

0 (B_0x0): activity state 0 is the initial activity state of this I3C before and when becoming controller

1 (B_0x1): activity state 1 is the initial activity state of this I3C when becoming controller

2 (B_0x2): activity state 2 is the initial activity state of this I3C when becoming controller

3 (B_0x3): activity state 3 is the initial activity state of this I3C when becoming controller

FMT

GETMXDS CCC format

0 (B_0x0): format 1 (2 bytes with MaxWr with no defining byte, MaxRd)

1 (B_0x1): format 2: (5 bytes w.ith MaxWr with no defining byte, MaxRd, MaxRdTurn)

2 (B_0x2): format 2 (5 bytes with MaxWr with no defining byte, MaxRd, and middle byte of MaxRdTurn)

3 (B_0x3): format 2 (5 bytes with MaxWr with no defining byte, MaxRd, MSB of MaxRdTurn)

RDTURN

programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte)

TSCO

clock-to-data turnaround time (t less than sub>SCO less than /sub>)

0 (B_0x0): t less than sub>SCO less than /sub> less than or equal 12 ns

1 (B_0x1): t less than sub>SCO less than /sub> > 12 ns (refer to the datasheet for more details)

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