stm32 /stm32n6 /STM32N645 /I3C1 /I3C_TIMINGR0

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Interpret as I3C_TIMINGR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SCLL_PP0SCLH_I3C0SCLL_OD0SCLH_I2C

Description

I3C timing register 0

Fields

SCLL_PP

SCL low duration in I3C push-pull phases, in number of kernel clocks cycles:

SCLH_I3C

SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles:

SCLL_OD

SCL low duration in open-drain phases, used for legacy I less than sup>2 less than /sup>C messages and for I3C open-drain phases (address phase following a start, ACK phase during controller-initiated messages, and T bit phase during direct/private/IBI payload), in number of kernel clocks cycles:

SCLH_I2C

SCL high duration, used for legacy I less than sup>2 less than /sup>C messages, in number of kernel clocks cycles:

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