STALLT=B_0x0, STALLC=B_0x0, STALLA=B_0x0, STALLD=B_0x0
I3C timing register 2
| STALLT | Controller clock stall enable on T-bit phase of data (and on the ACK/NACK phase of data byte of a legacy I less than sup>2 less than /sup>C read) 0 (B_0x0): no stall 1 (B_0x1): stall enabled |
| STALLD | Controller clock stall enable on PAR phase of Data 0 (B_0x0): no stall 1 (B_0x1): stall enabled |
| STALLC | Controller clock stall enable on PAR phase of CCC 0 (B_0x0): no stall 1 (B_0x1): stall enabled |
| STALLA | Controller clock stall enable on ACK phase 0 (B_0x0): no stall 1 (B_0x1): stall enabled |
| STALL | Controller clock stall time, in number of kernel clock cycles |